1. Field of the Invention
Embodiments of the invention relate to semiconductor memory devices. More particularly, embodiments of the invention relate to a flash memory device for an over-sampling read operation on a memory cell and an associated interfacing method.
2. Discussion of Related Art
Semiconductor memory devices are largely classified into volatile and non-volatile devices. Volatile semiconductor memory devices are characterized by fast reading and writing speeds, but the stored contents disappear when no external power is applied. In contrast, non-volatile semiconductor memory devices retain their stored contents even when no power is applied. Therefore, non-volatile semiconductor memory devices are used to store vital contents which must remain regardless of whether or not power is supplied to the device. Examples of non-volatile semiconductor memory devices include, for example, mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM).
Since erase and write operations are relatively complicated in MROM, PROM, and EPROM devices, memory contents may not be able to be updated. Because erase and write operations can be electrically done in EEPROM devices, these devices are more commonly used in system programming or auxiliary memory device applications which require continuous updating. Flash EEPROM devices have a higher degree of system integration compared to a typical EEPROM device because of its high-capacity memory applications. A NAND-type flash EEPROM (hereinafter, referred to as a NAND flash memory) has a remarkably higher degree of systems integration compared to other flash EEPROM.
As demands for memory capacity increases, devices that store multi-bit data in one memory cell are actively under development. When storing 1-bit data in a memory cell, the memory cell has two threshold voltage distributions; one voltage threshold corresponds to a data 1 and the other voltage threshold corresponds to a data 0. However, when storing 2-bit data in a single memory cell, the cell is programmed with one of four threshold voltage distributions. Additionally, when storing 3-bit data in a single memory cell, a memory cell is programmed with one of eight threshold voltage distributions. Recently, various technologies for storing 4-bit data on one memory cell are actively under development.
FIG. 1a is a diagram illustrating a normal read operation of a typical multi-bit memory cell where read voltages 10 are used to read multi-bit data in a memory cell allocated between threshold voltage distributions corresponding to 3-bit data (i.e., ‘111’, ‘110’, ‘101’, . . . , ‘001’, ‘000’), respectively. Read voltage Vrd3 is applied to a word line of a memory cell to read data of a most significant bit (MSB) page (e.g., a first page) of 3-bit data. A read voltage Vrd1 or Vrd5 is applied to read data of a second page between the MSB page and a least significant bit (LSB) page (e.g., a third page). Lastly, read voltages Vrd0, Vrd2, Vrd4, and Vrd6 are applied to a word line of memory cells to read data of the LSB page.
Accurate control of a program voltage Vpgm and a verify voltage Vvfy is essential to storing multi-bit data in one memory cell. Each interval between threshold voltage distributions in memory cells can be densely controlled by accurately controlling the voltage. In particular, a step size of a program voltage can be reduced for dense threshold voltage distributions. However, this drastically decreases program speed. Otherwise, threshold voltage distributions of memory cells can be formed in a broader voltage range. A high voltage pump is required to accommodate this broader voltage range which in turn, increases device costs. Attempts to resolve the above limitations are typically targeted at the read operation rather than the program operation. One attempt focuses on an over-sampling read operation or a fractional read operation through a maximum likelihood method. The over-sampling read operation utilizes a relative interval from a reference value of the threshold voltage distribution (e.g., a middle value of threshold voltage distribution).
FIG. 1b is a diagram illustrating an over-sampling read operation of a multi-bit memory cell. Over-sampling read voltages Vfrd0 to Vfrd7 are set within each threshold voltage distribution not between threshold voltage distributions as illustrated in FIG. 1a. An over-sampling voltage is applied to perform an over-sampling read operation one time with respect to one threshold voltage distribution. Accordingly, the respective over-sampling read voltages Vfrd0 to Vfrd7 are set with middle values (or, average values) of corresponding threshold voltage distributions. However, when performing an over-sampling read operation two or three times with respect to one threshold voltage distribution, over-sampling read voltages are set with values that equally divide one threshold voltage distribution into a plurality of units.
By utilizing a normal read operation and an over-sampling read operation, the read operation can be performed using a relative interval from a reference value of a threshold voltage distribution (e.g., an average value of distribution). Over-sampling read or fractional read operations are disclosed in U.S. Pat. No. 7,023,735 entitled “METHODS OF INCREASING THE RELIABILITY OF A FLASH MEMORY” and Japanese Patent Publication No. 2001-101879 entitled “SEMICONDUCTOR MEMORY DEVICE”, which are incorporated by reference. Accordingly, there is a need for a device or method for outputting over-sampling data.